module axi_slave #(
    parameter DATA_WIDTH = 128,  // 改为128位以匹配AXI master
    parameter ADDR_WIDTH = 32
)(
    // Global signals
    input wire ACLK,
    input wire ARESETN,  // Asynchronous reset signal

    // Write address channel
    input wire [ADDR_WIDTH-1:0] AWADDR,
    input wire [7:0] AWLEN,
    input wire [2:0] AWSIZE,
    input wire [1:0] AWBURST,  // Burst type: 00=FIXED, 01=INCR, 10=WRAP
    input wire AWVALID,
    output reg AWREADY,  // 改为reg
    
    // Write data channel
    input wire [DATA_WIDTH-1:0] WDATA,
    input wire [DATA_WIDTH/8-1:0] WSTRB,
    input wire WLAST,
    input wire WVALID,
    output reg WREADY,  // 改为reg
    
    // Write response channel
    output reg [1:0] BRESP,  // 改为reg
    output reg BVALID,  // 改为reg
    input wire BREADY,

    // Read address channel
    input wire [ADDR_WIDTH-1:0] ARADDR,
    input wire [7:0] ARLEN,
    input wire [2:0] ARSIZE,
    input wire [1:0] ARBURST,  // Burst type: 00=FIXED, 01=INCR, 10=WRAP
    input wire ARVALID,
    output reg ARREADY,  // 改为reg

    // Read data channel
    output reg [DATA_WIDTH-1:0] RDATA,  // 改为reg
    output reg [1:0] RRESP,  // 改为reg
    output reg RLAST,  // 改为reg
    output reg RVALID,  // 改为reg
    input wire RREADY
);
    // Internal signals
    reg [7:0] burst_counter;
    reg [ADDR_WIDTH-1:0] current_addr;  // Current address for burst operations

    // RAM interface signals
    //reg ram_we, ram_re;  // 改为reg
    reg [9:0] ram_addr;  // RAM地址宽度为10位，改为reg
    reg [31:0] ram_din;  // 改为reg
    wire [31:0] ram_dout;  // 保持wire，因为是RAM的输出
    reg [7:0] ram_burst_len;  // 改为reg
    wire ram_burst_done;  // 保持wire，因为是RAM的输出

    // 数据宽度转换：128位AXI数据转换为32位RAM数据
    reg [31:0] axi_data_buffer [0:3];  // 存储128位数据的4个32位部分
    reg [1:0] data_word_counter;  // 跟踪当前处理的是128位数据的哪个32位部分
    reg write_burst_active;
    reg [7:0] write_burst_counter;

    // State machine for write and read operations
    localparam IDLE = 2'b00;
    localparam WRITE = 2'b01;
    localparam READ = 2'b10;
    reg [1:0] current_state, next_state;

    // State transition logic
    always @(posedge ACLK or negedge ARESETN) begin
        if (!ARESETN) begin
            current_state <= IDLE;
        end else begin
            current_state <= next_state;
        end
    end

    // Next state logic
    always @(*) begin
        next_state = current_state;
        case (current_state)
            IDLE: begin
                if (AWVALID) begin
                    next_state = WRITE;
                end else if (ARVALID) begin
                    next_state = READ;
                end
            end
            WRITE: begin
                if (WVALID && WLAST && write_burst_active && ram_burst_done) begin
                    next_state = IDLE;
                end
            end
            READ: begin
                if (RVALID && RLAST) begin
                    next_state = IDLE;
                end
            end
        endcase
    end

    // Write address channel handshake
    always @(posedge ACLK or negedge ARESETN) begin
        if (!ARESETN) begin
            AWREADY <= 1'b0;
            current_addr <= {ADDR_WIDTH{1'b0}};
            write_burst_active <= 1'b0;
            write_burst_counter <= 8'b0;
        end else if (current_state == IDLE && AWVALID) begin
            AWREADY <= 1'b1;
            current_addr <= AWADDR;
            write_burst_active <= 1'b1;
            write_burst_counter <= 8'b0;
        end else begin
            AWREADY <= 1'b0;
        end
    end

    // Write data channel handshake and data processing
    always @(posedge ACLK or negedge ARESETN) begin
        if (!ARESETN) begin
            WREADY <= 1'b0;
            data_word_counter <= 2'b00;
            //ram_we <= 1'b0;
        end else if (current_state == WRITE && WVALID && write_burst_active) begin
            WREADY <= 1'b1;
            
            // 将128位数据分解为4个32位数据
            axi_data_buffer[0] <= WDATA[31:0];
            axi_data_buffer[1] <= WDATA[63:32];
            axi_data_buffer[2] <= WDATA[95:64];
            axi_data_buffer[3] <= WDATA[127:96];
            
            // 启动RAM写突发
            if (data_word_counter == 2'b00) begin
                //ram_we <= 1'b1;
                ram_addr <= current_addr[11:2];  // 将AXI地址转换为RAM地址
                ram_din <= WDATA[31:0];
                ram_burst_len <= 8'd3;  // 4个32位数据，突发长度为4-1=3
                data_word_counter <= 2'b01;
            end else if (data_word_counter == 2'b01) begin
                ram_din <= WDATA[63:32];
                data_word_counter <= 2'b10;
            end else if (data_word_counter == 2'b10) begin
                ram_din <= WDATA[95:64];
                data_word_counter <= 2'b11;
            end else if (data_word_counter == 2'b11) begin
                ram_din <= WDATA[127:96];
                data_word_counter <= 2'b00;
                //ram_we <= 1'b0;
                
                // 更新地址用于下一个128位数据
                case (AWBURST)
                    2'b00: current_addr <= current_addr;  // FIXED
                    2'b01: current_addr <= current_addr + 16;  // INCR: 128位=16字节
                    2'b10: begin  // WRAP
                        if (current_addr + 16 > AWADDR + (AWLEN << AWSIZE)) begin
                            current_addr <= AWADDR;
                        end else begin
                            current_addr <= current_addr + 16;
                        end
                    end
                    default: current_addr <= current_addr;
                endcase
                
                write_burst_counter <= write_burst_counter + 1;
            end
        end else begin
            WREADY <= 1'b0;
            //ram_we <= 1'b0;
        end
    end

    // Write response channel
    always @(posedge ACLK or negedge ARESETN) begin
        if (!ARESETN) begin
            BVALID <= 1'b0;
            BRESP <= 2'b00;
        end else if (WVALID && WLAST && write_burst_active && ram_burst_done) begin
            BVALID <= 1'b1;
            BRESP <= 2'b00; // OKAY response
            write_burst_active <= 1'b0;
        end else if (BREADY && BVALID) begin
            BVALID <= 1'b0;
        end
    end

    // Read address channel handshake
    always @(posedge ACLK or negedge ARESETN) begin
        if (!ARESETN) begin
            ARREADY <= 1'b0;
        end else if (current_state == IDLE && ARVALID) begin
            ARREADY <= 1'b1;
        end else begin
            ARREADY <= 1'b0;
        end
    end

    // Read data channel
    always @(posedge ACLK or negedge ARESETN) begin
        if (!ARESETN) begin
            RVALID <= 1'b0;
            RLAST <= 1'b0;
            RDATA <= {DATA_WIDTH{1'b0}};
            RRESP <= 2'b00;
            burst_counter <= 8'b0;
        end else if (current_state == READ) begin
            if (ARVALID && ARREADY) begin
                RVALID <= 1'b1;
                RLAST <= (burst_counter == ARLEN);
                RDATA <= {DATA_WIDTH{1'b1}}; // Example data
                RRESP <= 2'b00; // OKAY response
                burst_counter <= burst_counter + 1;
            end else if (RREADY && RVALID) begin
                if (RLAST) begin
                    RVALID <= 1'b0;
                    RLAST <= 1'b0;
                    burst_counter <= 8'b0;
                end
            end
        end
    end

    /* // 实例化RAM模块
    ram_32x1024_burst #(
        .DATA_WIDTH(32),
        .ADDR_WIDTH(10),
        .DEPTH(1024)
    ) ram_inst (
        .clk(ACLK),
        .rst_n(ARESETN),
        .we(ram_we),
        .re(ram_re),
        .addr(ram_addr),
        .din(ram_din),
        .burst_len(ram_burst_len),
        .dout(ram_dout),
        .burst_done(ram_burst_done)
    ); */

/*     // 读使能信号（当前未使用，但保留接口）
    always @(posedge ACLK or negedge ARESETN) begin
        if (!ARESETN) begin
            ram_re <= 1'b0;
        end else begin
            ram_re <= 1'b0;  // 当前只实现写功能
        end
    end */
endmodule